1. Field of the Invention
The present invention relates to an apparatus and method for minimizing the power dissipation and delay times in logic circuit devices. The invention has particularly application in large scale integrated circuits (LSIs) and very large scale integrated circuits (VLSIs) which are designed using computer aided design (CAD) systems.
2. Description of Related Art
In recent years, portable electric equipment and the batteries used therein are rapidly becoming smaller in size. Thus, it is important that the logic LSIs and VLSIs integrated circuits used in such devices have low power dissipation. Moreover, counter measures against heat dissipation has become very important in recent years for high-performance ICs which operate at frequency in the several hundred MHZ range. Accordingly, implementing a method to minimize heat dissipating is extremely important.
It is well known that most of the power in an IC is used for the charge and discharge cycle of the capacitance load when N channel MOS transistors and P channel MOS transistors are switched in CMOS circuits in LSIs and VSLIs devices. Therefore, it is necessary to consider a reduction in the power dissipation of switching transistors in order to achieve a lower power dissipation.
Generally, power dissipation P required for a CMOS circuit's switching operation is shown in Equation (1) below: EQU P=f.multidot.V.sup.2 .multidot.(.SIGMA..alpha.(i).multidot.C(i))EQUATION 1
where the frequency of the system clock signal is f, the power supply voltage is V, .alpha.(i) is the switching ratio at a node i, and C(i) is a load capacitance at the same note i.
Analyzing Equation (1) suggests various ways for achieving a lower power dissipation. The most basic method is to minimize the individual parameters in Equation (1). For example, lowering the system clock signal frequency or the power supply voltage results in a reduction in power dissipation. Lowering the power supply voltage is especially effective because it can reduce the power dissipation in square proportion. Doing so, however, causes performance deterioration at the same time. Thus, lowering the power supply voltage is not an effective solution in all cases. The ideal solution for achieving low power dissipation should not result in a deterioration in performance of the IC.
Another method of reducing power dissipation is to reduce the switching ratio .alpha.(i) at each node. This method inhibits the activation of unnecessary portions of the device in accordance with the operation required to be performed by the device. For example, one such method relies on the use of activation signals for the clock signal. Since this method depends largely on system operation, its effectiveness is often determined by the way in which it is implemented by the IC designer. Moreover, implementation of such a method is often a manual process which depends to a great extent on the knowledge, skill and training of the design engineers. A manual process naturally leads to an inefficient implementation.
Another technique used to lower power dissipation is to reduce load capacity C(i). The load capacity C(i) is shown by Equation (2) below: EQU C(i)=Cd(i)+Cw(i)+Cg(i) EQUATION 2
where Cd(i) is the diffusion capacitance, Cw(i) is the wiring capacitance, and Cg(i) is the gate capacitance. This method is often implemented using CAD tools because to do so, eliminates the inefficiencies associated with a manual implementation and makes it much easier to observe restrictions on circuit timing.
CAD tools for IC design have improved greatly in recent years and generally fall into two categories, the ones at the element level and the ones at the basic cell-base level. The element level refers to a semiconductor element, for example, a transistor, and the basic cell level refers to a set of elements which perform a function, for example, a NAND gate.
The cell-based processing methods include, for example, the following steps:
(1) preparing basic cells formed of elements with small gate widths or size; PA1 (2) analyzing the design layout to replace basic cells with ones having smaller gate widths; and PA1 (3) replacing smaller cells with even smaller cells within the range of the design restrictions.
The element-based processing method is based on minimizing the diffusion capacitance Cd(i) and the gate capacitance Cw(i) as much as possible without adversely effecting required circuit characters, such as timing. Circuit timing is analyzed after designing with minimum size elements and the size of some elements are then increased as required in order to correct for adverse timing effects. This operation is repeated until the results of the analysis meet the design requirements.
Recently, a method of reducing power dissipation using several levels of power supply voltages at each node was proposed. In this method, power dissipation P is shown in Equation (3). EQU P=f.multidot.(.SIGMA.V(i).sup.2 .multidot..alpha.(i).multidot.C(i))EQUATION 3
This method is similar to the method used to reduce load capacity C(i) at a point that V(i) is determined by each node after analyzing circuit timing.
The low power dissipation methods used to minimize parameters independently as described above can be expected to show some beneficial effect. However, such methods are not entirely effective. In order to obtain a sufficient result, the load capacitance of the most frequently operating node in actual circuit operation should be made as small as possible. Thus, it is required to optimize .alpha.(i).multidot.C(i) at each node while at the same time meeting timing restrictions and other requirements of the circuit.
The CAD tools for IC circuit design have improved for static optimization, such as a method based on adjusting the load capacitance, as well as for active optimization, such as a method based on adjusting the combination of the layout data and the switching rate of each node in actual circuit operation. However, there is no established method to achieve lower power dissipation in large scale circuits taking into consideration circuit timing restriction.
Although shrinking device size can reduce both load capacitance and power dissipation in general, the device minimization causes the operating speed to be reduced and increases the delay time. Therefore, it is important to adjust the device size to reduce power dissipation while preventing an increase in circuit delay time.